Silicon carbide (SiC) is a hard semiconductor material with a larger bandgap than silicon (Si), and it has been applied to various semiconductor devices such as power devices, hostile-environment devices, high-temperature devices, and high-frequency devices. Applications to power devices such as semiconductor devices and rectifier devices, among others, have been drawing public attention. Power devices using SiC have advantages such as the significant decrease in power loss as compared with Si power devices. Utilizing such characteristics of SiC power devices, it is possible to realize smaller semiconductor devices as compared with Si power devices.
Of all power devices using SiC, one of typical semiconductor devices is metal-insulator-semiconductor field effect transistors (MISFETs). Hereinafter, a MISFET using SiC may be referred to simply as “SiC-FET”. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of MISFETs.
In order for an even higher current to flow through a power device such as a MISFET, it is effective to increase the channel density. Therefore, vertical MISFETs having the trench gate structure (trench-type MISFETs) have been proposed, replacing the conventional vertical MISFETs having the planar structure (planar-type MISFETs).
In a trench-type MISFET, the channel region is formed on the side surface of the trench formed in the semiconductor layer. Therefore, the channel packing density for the substrate area can be improved sufficiently, and the ON resistance (normalized ON resistance) per unit area can be sufficiently decreased.
Now, referring to FIG. 47, an example of a cross-sectional structure of a conventional trench-type MISFET will be described. The trench-type MISFET shown in FIG. 47 is disclosed in Patent Document No. 1, for example. A vertical MISFET typically includes a plurality of unit cells arranged in two dimensions.
A semiconductor device 1000 shown in FIG. 47 includes a plurality of unit cells 1000u. Each unit cell 1000u includes an n+-type substrate 1010 of silicon carbide, and a silicon carbide semiconductor layer 1020 formed on the principal surface of the substrate 1010. The silicon carbide semiconductor layer 1020 includes an n−-type drift region 1020d formed on the principal surface of the substrate 1010, and a p-type body region 1030 formed on the drift region 1020d. A p+-type contact region 1050 and an n+-type source region 1040 are arranged in a portion of the surface region of the body region 1030. A source electrode 1090 is arranged on the silicon carbide semiconductor layer 1020 so as to be in contact with the contact region 1050 and the source region 1040.
A trench 1020t is arranged in the silicon carbide semiconductor layer 1020 so as to run through the body region 1030 to reach the drift region 1020d. In this example, the trench 1020t runs through the source region 1040 and the body region 1030 to reach the drift region 1020d. An n−-type channel layer 1060 is arranged on the side wall of the trench 1020t so as to connect between the source region 1040 and the drift region 1020d. Arranged in the trench 1020t are a gate electrode 1080, and a gate insulating film 1070 for providing insulation between the gate electrode 1080 and the channel layer 1060. A drain electrode 1100 is provided on the reverse surface of the substrate 1010.
An interlayer insulating film 1110 is formed on the source electrode 1090 and the gate electrode 1080. An upper wiring electrode 1120 is provided on the interlayer insulating film 1110. The upper wiring electrode 1120 is electrically connected to the source electrode 1090 of each unit cell 1000u in an opening portion 1110c formed in the interlayer insulating film 1110. A reverse surface wiring electrode 1130 is provided on the drain electrode 1100. When mounted onto a lead frame or a module, the reverse surface wiring electrode 1130 serves to provide adhesion between the semiconductor device 1000 and a solder material for securing the lead frame or the module.
Patent Document No. 2 discloses an example where the channel layer 1060 is of the p-type.
Patent Document No. 3 discloses a MISFET serving as a diode for allowing a current to flow from the source electrode 1090 to the drain electrode 1100 through the channel layer 1060.